1. Field of the Invention
Aspects of the present invention relate to a driving circuit and an organic electroluminescence display using the same, and more specifically, to a driving circuit capable of decreasing a gray level error to improve linearity by preventing a voltage drop generated in an analog switch, and an organic electroluminescence display using the same.
2. Description of the Related Art
A flat panel display has a plurality of pixels arranged in a matrix type pattern on a substrate as a display area, and a scan line and a data line connected to each pixel to display an image by selectively applying a data signal to the pixels.
Flat panel displays are classified into passive matrix-type light-emitting displays and active matrix-type light-emitting displays according to a driving mode of respective pixels. The active matrix-type light-emitting displays which turn on the light by individual pixels has been mainly used terms of a high resolution, good contrast and fast operating speed.
Active matrix flat panel displays have been used as displays in such applications as personal computers, portable phones, PDAs, etc., or as monitors of various information appliances, and active matrix flat panel displays have been fabricated of liquid crystal displays (LCDs) using a liquid crystal panel, organic electroluminescence displays using an organic electroluminescence devices, plasma display panels (PDPs) using plasma panels, etc., as have been known in the art.
Recently, various light-emitting displays having a smaller weight and volume than a cathode ray tube have been developed, and attention has been particularly paid to the organic electroluminescence display which exhibits excellent luminous efficiency, a luminance and viewing angle and has a rapid response time.
FIG. 1 is a circuit view showing a configuration of a conventional organic electroluminescence display 10. Referring to FIG. 1, the organic electroluminescence display includes a pixel unit 100, a data driving unit 200 and a scan driving unit 300.
The pixel unit 100 includes a plurality of data lines (D1,D2 . . . Dm−1,Dm) and a plurality of scan lines (S1,S2 . . . Sn−1,Sn), and a plurality of pixels formed in a region defined in a plurality of the data lines (D1,D2 . . . Dm−1,Dm) and a plurality of the scan lines (S1,S2 . . . Sn−1,Sn). The pixel 101 includes a pixel circuit and an organic electroluminescence device, and the pixel 101 generates a pixel current in the pixel circuit to flow to the organic electroluminescence device, the pixel current flows in the pixels according to data signals transmitted through a plurality of the data lines (D1,D2 . . . Dm−1,Dm) and scan signals transmitted through a plurality of the scan lines (S1,S2 . . . Sn−1,Sn).
The data driving unit 200 is connected with a plurality of the data lines (D1,D2 . . . Dm−1,Dm), and generates data signals to sequentially transmit a row of data signals to a plurality of the data lines (D1,D2 . . . Dm−1,Dm). The data driving unit 200 also has a (digital-to-analog) (D/A) converter, and generates a gray level voltage which is converted from a digital signal into an analog signal by the D/A converter, thereby to transmit the gray level voltage to the data lines (D1,D2 . . . Dm−1,Dm).
The scan driving unit 300 is connected to a plurality of scan lines (S1,S2 . . . Sn−1,Sn), and generates a scan signal to transmit the scan signal to a plurality of the scan lines (S1,S2 . . . Sn−1,Sn). A certain row is selected by the scan signals, and a data signal is transmitted to a pixel 101 arranged in the selected row, such that a current corresponding to the data signal is generated in the pixel.
FIG. 2 is a circuit view showing a resistance unit which generates a gray level voltage in a conventional D/A converter. Referring to FIG. 2, assume that the resistance unit generates eight gray level voltages for illustration. In order to generate eight gray level voltages, eight resistances (R1, R2, . . . R8) are connected in series, and a first reference voltage having a high voltage (VrefH) and a second reference voltage having a low voltage (VrefL) are respectively transmitted to both ends of the resistances connected in series, and then the first reference voltage and the second reference voltage become a gray level voltage distributed by the eight resistances. At this time, the first reference voltage and the second reference voltage are selected from a plurality of voltages, and a voltage drop is generated in switches due to an error of resistances in an ON state of the switches which select each of the first reference voltages and the second reference voltages, resulting in generation of an offset voltage. Also, a plurality of the first reference voltages and a plurality of the second reference voltages are not made linear due to the resistance differences of the switches which select the first reference voltage and the second reference voltage.